Lead Engineer

DAVRON CV: Candidate 1932083

HARDWARE & ASIC ARCHITECT | FPGA/ASIC DESIGN, FIRST-SILICON SUCCESS, MULTIDISCIPLINARY ENGINEERING LEADER

Core Expertise

• Mixed-signal ASIC architecture and gate-level design with first-silicon success and zero re-spins.
• FPGA development and verification strategy including test-vector generation and HDL-based testbenches.
• Cross-functional hardware, firmware, optics, mechanical, and manufacturing program leadership.
• Design-for-manufacturability, yield optimization, and offshore manufacturing setup with sustaining engineering.
• Field reliability, product readiness, and test engineering for high-reliability systems.

Project Background

• Sole designer of a production mixed-signal ASIC maintained in continuous manufacture for 26+ years, deployed in millions of units.
• Led multidisciplinary engineering teams of up to 14 across new-product development and sustaining engineering.
• Founded and scaled a test engineering department owning product readiness and global field retrofit programs.
• Executed logic consolidation and verification for legacy high-reliability military fire-control systems using FPGA replacements.
• Delivered Class III medical-device test systems and mission-critical automated test engineering for regulated manufacturing.

Key Skills

• ASIC & FPGA architecture | Gate-level design | First-silicon discipline
• HDL | Verilog/VHDL | 8051 firmware | C++ | Mentor Graphics
• Verification strategy | Test-vector generation | HDL-based testbenches
• DFM & yield optimization | Asynchronous BIST design
• Program management | Cross-functional leadership | Offshore manufacturing & sustaining engineering
• Field reliability engineering | Product readiness | Test engineering

Education

• A.A.S., Electronics Technology with Engineering Emphasis — Arapahoe Community College
• Graduate-level engineering coursework (company-sponsored continuing-education program) — Colorado State University

Awards & Recognition

• Named inventor on multiple U.S. patents for sensing, imaging, and position-sensor technologies

Why Interview this Candidate?

A seasoned hardware and ASIC architect who delivered a production mixed-signal ASIC with zero re-spins and multi-million unit deployment. They compress schedules through concurrent design-and-verification, lead multidisciplinary teams across hardware, firmware, optics, and manufacturing, and establish test and sustaining practices that maximize field reliability. Ideal for senior engineering leadership or lead hardware roles needing hands-on first-silicon and test-engineering expertise.